All silicon capacitive pressure sensor

ABSTRACT

A configuration for a capacitive pressure sensor uses a silicon on insulator wafer to create an electrically isolated sensing node across a gap from a pressure sensing wafer. The electrical isolation, small area of the gap, and silicon material throughout the capacitive pressure sensor allow for minimal parasitic capacitance and avoid problems associated with thermal mismatch.

BACKGROUND

Microelectromechanical systems (MEMS) are small devices made ofelectrical and mechanical components, designed to work together to sensephysical properties in their local environment. For instance, MEMSpressure sensors are designed to sense and report the pressure of afluid or environment in which the pressure sensor resides. MEMS pressuresensors can be capacitive pressure sensors.

Capacitive pressure sensors are made of two electrodes separated by agap. When pressure is applied to a pressure diaphragm, the diaphragmdeforms and the gap changes, allowing the pressure sensor to detect thepressure change. The two electrodes must be electrically separated forthe capacitive pressure sensor to work.

Traditional capacitive pressure sensors use two wafers made of differentmaterials for the electrode assembly, typically silicon for thediaphragm electrode wafer, and an insulator, such as glass, for thesecond electrode wafer. The glass electrode wafer is metalized toprovide a conductive path for the second electrode. However, these typesof capacitive pressure sensors result in thermal mismatch between theglass electrode wafer and the silicon electrode wafer it is attached to.Moreover, glass tends to move or creep, creating thermal hysteresiseffects in devices. These characteristics cause errors which reduce theaccuracy of the pressure sensor.

Other capacitive pressure sensors use an all silicon second electrode byusing a silicon on insulator (“SOT”) wafer. In this type of arrangement,the second electrode is silicon separated from the first electrode by athin dielectric layer, typically an oxide. While this arrangement avoidssome of the pitfalls of a glass electrode, it has large parasiticcapacitance, resulting in signal dilution. This occurs due to both thehigh permittivity of oxides and large bond area between the wafers.Additionally, the structure of diaphragm based capacitive pressuresensors results in the maximum gap deflection on only the small centralportion of the diaphragm. This small area between the first and secondelectrode is the only useful area for measuring pressure, the rest ofthe area contributes to the parasitic capacitance.

Ideally, a capacitive pressure sensor design should avoid thermalmismatch between materials and minimize parasitic capacitance.

SUMMARY

A capacitive pressure sensor includes a backing wafer; a sensing wafercomprising: a support portion bonded to the backing wafer, and a sensingportion, the sensing portion configured to detect pressure; an electrodeassembly comprising: a first silicon layer comprising: an attachmentportion bonded to the sensing wafer; and a sensing node, the sensingnode centered over the sensing portion of the sensing wafer, wherein thesensing node is isolated from the sensing portion of the sensing waferby a gap, and wherein the sensing node is isolated from the attachmentportion of the first silicon layer by a separation area; an insulatinglayer bonded to the first silicon layer opposite the sensing wafer; anda second silicon layer bonded to the insulating layer opposite the firstsilicon layer, the second silicon layer comprising: a first electricalcontact electrically connected with the sensing wafer; and a secondelectrical contact electrically connected with the sensing node.

A method of making a capacitive pressure sensor includes depositing anitride layer on a silicon on insulator wafer; etching a sensing node ona first side of the silicon on insulator wafer; etching primary andsecondary cavities on a second side of the silicon on insulator waferopposite the first side; selectively removing the protective nitridelayer; bonding a sensing wafer to the first side of the silicon oninsulator wafer opposite the second side; bonding a backing wafer to thesensing wafer opposite the silicon on insulator wafer; and depositingmetal onto the primary cavities.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic diagram of a glass electrode capacitive pressuresensor as found in prior art.

FIG. 1B is a schematic diagram of a simple silicon on insulatorcapacitive pressure sensor as found in prior art.

FIG. 2 is a schematic diagram of an all silicon capacitive pressuresensor.

FIG. 3 is a schematic diagram of an all silicon capacitive pressuresensor with a reference node.

FIG. 4 is a schematic diagram of an all silicon capacitive pressuresensor with integrated electronics.

FIG. 5 is a schematic diagram of a method of making an all siliconcapacitive pressure sensor.

DETAILED DESCRIPTION

An all silicon capacitive pressure sensor can solve both thermalmismatch issues and high parasitic capacitance problems presented inprior art capacitive pressure sensor designs. An electrically isolatedsilicon sensing node acting as one half of the capacitor allows forthese benefits. The silicon sensing node is electrically isolated fromboth conductive and capacitive losses.

FIG. 1A is a schematic diagram of one example of capacitive pressuresensor 10 found in the prior art. Capacitive pressure sensor 10 includesbacking wafer 12, sensing wafer 14, glass electrode wafer 16, siliconelectrode 18, and gap 20. Backing wafer 12 is bonded to sensing wafer14, and sensing wafer 14 is bonded to glass electrode wafer 16. Gap 20is present between electrodes 16 and 18. Glass electrode 16 containsmetallization 28. Metallization 28 is continuous through via 29 to bringelectrical connection of electrode gap 20 to the top surface.

Backing wafer 12 and sensing wafer 14 are made of silicon. Backing wafer12 is designed to anchor and protect sensing wafer 14. Silicon electrode18 is attached to sensing wafer 14. Silicon electrode 18 can be a highlydoped conductive region in sensing wafer 14, or alternately all ofsensing wafer 14 can be highly doped and considered conductive. Sensingwafer 14 contains central diaphragm portion 22 and outer support portion24. Diaphragm portion 22 of sensing wafer 14 is aligned withmetallization via 29.

Metallization via 29 provides a path for glass electrode metallization28 to connect the gap region 20 with top surface of glass electrodewafer 16. Diaphragm portion 22 of sensing wafer 14 deflects withpressure (represented by arrow P) from an external environment, but isprotected from the external environment by backing wafer 12. Whendiaphragm portion 22 of sensing wafer 14 deflects, it effects gap 20.

The change in gap 20 is detected by electrodes 16 and 18, which arefacing each other. Electrode 16 is made of glass or another insulator,and is attached directly to silicon sensing wafer 14. Thus, the bondbetween glass electrode wafer 16 and silicon sensing wafer 14 is subjectto thermal mismatch, which can cause significant stress on pressuresensor 10. Additionally, glass, due to its amorphous structure, has atendency to move or “creep” when subjected to varying temperature andpressure conditions. This causes the glass to change the distance of gap20, the connection of glass electrode 16 to sensing wafer 14, or otherconstants in pressure sensor 10. Electrode 18 is more conductive, and isusually a doped region in semiconducting silicon. When diaphragm portion22 deflects from incoming pressure, the distance between diaphragmportion 22 and glass electrode metallization 28 changes, resulting in achange of capacitance. The change in capacitance between the electrodes16 and 18 allows pressure sensor 10 to detect pressure. However, thedrawbacks of this set-up create unreliable pressure sensor data.

FIG. 1B is a schematic diagram of capacitive pressure sensor 30, anotherexample found in the prior art. Capacitive pressure sensor 30 includesbacking wafer 32, sensing wafer 34, oxide layer 36, silicon on insulator(SOI) electrode 38, and gap 40. Capacitive pressure sensor 30 is analternative to capacitive pressure sensor 10 in FIG. 1A, both found inthe prior art. In pressure sensor 30, backing wafer 32 is attached tosensing wafer 34, and SOI electrode 38 is bonded to sensing wafer 34along oxide layer 36. Gap 40 is located between sensing wafer 34 and SOIelectrode 38. Bond pads 46 allow for electrical connections to sensingwafer 34 and SOI electrode 34.

Backing wafer 32 and sensing wafer 34 are made of silicon. Backing wafer32 is designed to anchor and protect sensing wafer 34. Sensing wafer 34contains central diaphragm portion 42 and outer support portion 44.Diaphragm portion 42 of sensing wafer 34 is aligned with gap 40.Diaphragm portion 42 of sensing wafer 34 deflects with pressure from anexternal environment, but is protected from the external environment bybacking wafer 32. When diaphragm portion 42 of sensing wafer 34deflects, it affects gap 40.

The change in gap 40 between sensing wafer diaphragm 42 and SOIelectrode 38 is reflective of pressure detected by diaphragm 42.However, SOI electrode 38 is very close to sensing wafer 34, whichresults in a large parasitic capacitance. Parasitic capacitance, orstray capacitance, is an unwanted capacitance that exists betweenelectrical components. In pressure sensor 30, parasitic capacitancearises due to the thinness of oxide layer 36, which has high dielectricpermittivity and is used to bond sensing wafer 34 to SOI electrode 38.In pressure sensor 30, the parasitic capacitance is so high that it caninterfere with useful pressure signals. Additionally, the capacitanceincreases due to gap 40 being maintained along most of pressure sensor30, but only a small portion of gap 40 is useful for detectingdeflection of diaphragm 42.

FIG. 2 is a schematic diagram of all silicon capacitive pressure sensor50, which eliminates thermal mismatch and minimizes parasiticcapacitance common in prior art designs. Pressure sensor 50 includesbase wafer 52, backing wafer 54, sensing wafer 56 (which includessupport portion 58 and diaphragm 60), and electrode assembly 62.Electrode assembly 62 includes first silicon layer 64, second siliconlayer 66, and dielectric layer 68. Within first silicon layer 64 arestructural portions 70 and sensing node 72, separated by separationareas 74. Within second silicon layer 66 are electrical contacts 76, 77(which include metallic layer 78) and isolation cavities 80 separated bystructural portions 82.

Base wafer 52 serves as an anchor for pressure sensor 50, and isoptional depending on the needs of pressure sensor 50 and theenvironment in which it rests. Base wafer 52 can be made of aninsulator, such as glass, or other appropriate materials. Backing wafer54 is anchored to base wafer 52. Backing wafer 54 is made of silicon.Both base wafer 52 and backing wafer 54 serve to protect sensing wafer56 from the external environment. Base wafer 52 includes a passagethrough which fluid of interest can pass to backing wafer 54 and sensingwafer 56. Backing wafer 54 contains a small passage through which fluidcan pass to sensing wafer 56, protecting sensing wafer 56 from harshexternal environments. Base wafer 52 can also be used to anchor pressuresensor 50 in a housing (not pictured).

Sensing wafer 56 is also made of silicon, and is bonded to backing wafer54. Sensing wafer includes support portion 58 and diaphragm 60. Supportportion 58 stabilizes sensing wafer 56. Diaphragm 60 deflects based onincoming fluid pressure. Diaphragm 60 is aligned with sensing node 72 ofelectrode assembly 62 to create a capacitive pressure sensor. Gap 75between diaphragm 60 and sensing node 72 changes when diaphragm 60 isdeflected by pressure from a fluid of interest. Sensing wafer 56 isattached to electrode assembly 62, which includes sensing node 72.

Electrode assembly 62 is made of a silicon on insulator (SOI) materialwith two silicon layers 64, 66 and dielectric layer 68 (typically anoxide) between the first and second silicon layers. First layer 64 isattached directly to sensing wafer 56 through structural portions 70,which are bonded to support portions 58 of sensing wafer 56. First layer64 also contains sensing node 72, also made of silicon. Sensing node 72is centered in electrode assembly 62 over diaphragm 60 of sensing wafer56. Sensing node 72 is electrically isolated from sensing wafer 56 andstructural portions 58 by separation areas 74 and gap 75.

Separation areas 74 can be a vacuum or air insulation, depending on theneeds of pressure sensor 50. If areas 74 are a vacuum, the setupeliminates a need for expensive vacuum packing later. Gap 75 liesbetween diaphragm 60 and node 72, and changes as diaphragm 60 isdeflected. Node 72 detects the change in proximity of diaphragm 60across the gap and sends a signal through second electrical connection77, which is anchored in second layer 66 but runs through dielectriclayer 68 to be in electrical contact with node 72. Similarly, firstelectrical connection 76 extends through dielectric layer 68 and is inelectrical connection with structural portions 70 and sensing wafer 56.

Dielectric layer 68 is typically an oxide layer, and is electricallyisolating. Dielectric layer 68 ensures node 72 is not electricallyconnected to diaphragm 60, and that electrical contacts 76 are only incontact with the proper sources of electrical signal. Second layer 66,isolated from first layer 64 by dielectric layer 68, and contains one ormore electrical contacts 76, which are plated with a metal 78.Electrical contacts 76 are isolated from each other by isolation gaps 80and from other parts of electrode assembly 62 by dielectric layer 68.First and second electrical contact 76, 77 run through dielectric layer68 at certain areas to create electrical connections to either diaphragm60 (contact 76) or sensing node 72 (contact 77). Electrical contacts 76,77 can be connected to external electronics (not pictured).

The configuration of electrode assembly 62 allows for low parasiticcapacitance across gap 75, as gap 75 is small, central, and isolated byareas 74. In particular, a small bond area between structural portions70 and 82 (where support portions 82 overlap with sensing node 72)minimizes the contribution of parasitic capacitance due to that area.Generally, the bond length between structural portions 70 and 82 is nogreater than ten times the length of gap 75. Additionally, the width ofisolation cavities 80, and the width of separation areas 74 is greaterthan five times the width of gap 75. This reduces parasitic capacitancecontributed by isolation cavities 80 and separation areas 74.

Overall, parasitic capacitance due to dielectric layer 68 can be lessthan 10% of the base capacitance, which is minimal compared toarrangement found in the prior art. But the configuration of electrodeassembly 62 also allows for a reduction in thermal mismatch, becausestructural portions 70 and support portions 58, which attach sensingwafer 56 to electrode assembly 62, are all made of silicon.

FIG. 3 is a schematic diagram of all silicon capacitive pressure sensor90 with a reference node. Pressure sensor 90 is similar to pressuresensor 50 in FIG. 2, but contains a second node used as a reference.Pressure sensor 90 includes base wafer 92, backing wafer 94, sensingwafer 96, and electrode assembly 102. Electrode assembly 102, which isstill a silicon on insulator electrode, contains first layer 104, secondlayer 106, and dielectric layer 108. First layer 104 contains structuralportions 110, sensing node 112, and reference node 128. Second layer 106contains structural portions 122, electrical contacts 116, 117, 119, andisolation gaps 120.

Base wafer 92 and backing wafer 94 are similar to base wafer 52 andbacking wafer 54 in FIG. 2, function in the same way, and are attachedin the same manner. Sensing wafer 96, which is still made of silicon,contains support portions 98, sensing diaphragm 100, and referencediaphragm 126. Sensing wafer 96 is bonded to backing wafer 94. Sensingdiaphragm 100 is open to the external environment through passages inbase wafer 92 and backing wafer 94, and still deflects based on thepressure of the fluid of interest. Sensing diaphragm 100 is aligned withsensing node 112 of electrode assembly 102 across gap 115. Deflection ofdiaphragm 100 changes capacitance across gap 115 and allows node 112 todetect the change.

Reference diaphragm 126 does not deflect. Reference diaphragm 126 isaligned with reference node 128 of electrode assembly 102. Referencediaphragm 126 is separated from reference node 128 by gap 129. Gap 129serves as a point of reference for pressure detected at gap 115 betweendiaphragm 100 and node 112.

Electrode assembly 102 is similar to electrode assembly 62 in FIG. 2,with the addition of reference node 128 in first layer 104, andcorresponding electrical contacts in second layer 106. First layer 104contains structural portions 110, sensing node 112, and reference node128. Second layer 106 contains structural portions 122, electricalcontacts 116, 117, 119, and isolation gaps 120. First side 104 isseparated from second layer 106 by dielectric layer 108 (typically anoxide or other insulator).

Like FIG. 2, sensing node 112 is electrically isolated from structuralportions 110 and sensing wafer 96 by separation areas 114 and gap 115.Sensing node 112 is also electrically isolated from second layer 106 bydielectric layer 108. Similarly, reference node 128 is electricallyisolated from structural portions 110 and sensing wafer 96 byseparations areas 127 and gap 129. Reference node 128 is alsoelectrically isolated from second layer 106 by dielectric layer 108.

Second layer 106 contains one or more electrical contacts 116, which areplated with a metal 118. Electrical contacts 116, 117, 119 are isolatedfrom each other by isolation gaps 120 and from other parts of electrodeassembly 102 by dielectric layer 108. Electrical contacts 116, 117, 119run through dielectric layer 108 at certain areas to create electricalconnections to sensing wafer 96, sensing node 112, or reference node128. Electrical contacts 116, 117, 119 can be connected to externalelectronics (not pictured). In this set up, reference node 126 allows apoint of reference for capacitance from sensing node 100.

FIG. 4 is a schematic diagram of all silicon capacitive pressure sensor130 with integrated electronics. Pressure sensor 130 is similar topressure sensor 90 of FIG. 3, and has many of the same components,connected in the same manner, except where otherwise noted. FIG. 4 addstopping wafer assembly 132 to electrode assembly 102 opposite sensingwafer 96. Topping wafer assembly includes bonds 134, topping wafer 136,integrated circuit (IC) components 138, and wire bonds 142, 144.

Topping wafer 136 is bonded to electrode assembly 102 through bonds 134.Topping wafer 136 is typically made of silicon. Bonds 134 are structuraland electrically insulating. IC components 138 are bonded to toppingwafer 136. IC components 138 are electrically connected to electricalcontacts 116, 117 and 119 via wire bonds 142, 144. IC components 138receive electrical signals from electrical contacts 116 and amplify thesignals until the signals are useable. IC components 138 can then sendsignals to external electronics (not pictured).

FIG. 5 is a schematic diagram of method 150 of making an all siliconcapacitive pressure sensor. Method 150 begins with depositing a nitrideprotection layer on a silicon on insulator (SOI) wafer in steps 152 to158. Depositing a nitride protection layer begins with step 152 wherelow pressure chemical vapor deposition is performed, creating a nitridelayer on the external surfaces of the SOI wafer.

Next, in step 154, a portion on a first side of the SOI wafer ispatterned and a portion of the nitride layer is etched. Following this,in step 156, local oxidation of silicon etches a shallow cavity in theportion of the SOI wafer that was previously patterned and etched. Instep 158, the resulting oxide is stripped, and a nitride layer isdeposited to protect the etched surface.

After deposition of a nitride protection layer, cavities are etched intothe wafer in steps 160 to 162. First, in step 160, deep reactive ionetching is used to create cavities on the first side of the SOI waferaround the portion that was previously protected with a nitride layer,resulting in a node isolated by surrounding negative areas. Next, instep 162, multiple cavities are etched on a second side of the SOI wafer(opposite the first side), using deep reactive ion etching. In thisprocess, two types of cavities are etched: primary cavities andsecondary cavities. After etching, the nitride protection layer isselectively removed (or “stripped”) in step 164.

Next, the SOI wafer is bonded to a series of wafers that will make upthe pressure sensor as a whole in steps 166 to 168. First is a sensingwafer, made of silicon. The sensing wafer is vacuum fusion bonded to theSOI wafer on the first side of the SOI wafer in step 166. Next, in step168, a backing wafer, also made of silicon, is vacuum fusion bonded tothe sensing wafer opposite the SOI wafer. The fusion bonds are thenannealed to strengthen the bonds.

After the sensing wafer and backing wafer are attached, oxide isselectively removed from the assembly in step 170. After the removal ofoxide, in step 172, metal is deposited in the primary cavitiespreviously etched in the second side (opposite the sensing wafer) of theSOI wafer. Metal can be deposited through a shadow mask or via a liftoff photolithography technique.

Finally, in step 174, a glass base wafer is bonded to the backing waferopposite the sensing wafer. Metal can be deposited onto the base waferopposite the backing wafer for future attachment of the assembly toother packaging. The electrically isolated sensing node created in theSOI wafer and the electrical connection system allow for low parasiticcapacitance and minimal thermal mismatch.

The proposed capacitive pressure sensor is a low cost alternative toprevious versions. The internal vacuum on this design removes the needfor expensive vacuum packaging. Additionally, the proposed capacitivepressure sensor has high performance and low parasitic capacitance. Thesubstrate materials in this pressure sensor are thermally matched toavoid thermal stress caused by thermal mismatch. There is no creep ofelectrode material, nor is there any hysteresis associated withtraditional insulator electrodes. Moreover, the reduced bond areabetween electrodes and recessed electrode regions reduces parasiticcapacitance to less than 10% of base capacitance, resulting in moreaccurate pressure readings. Finally, this pressure sensor has highmaterial stability, as silicon is a highly stable crystalline materialthat is easily obtained at high purities.

Discussion of Possible Embodiments

The following are non-exclusive descriptions of possible embodiments ofthe present invention.

A capacitive pressure sensor includes a backing wafer; a sensing wafercomprising: a support portion bonded to the backing wafer, and a sensingportion, the sensing portion configured to detect pressure; an electrodeassembly comprising: a first silicon layer comprising: an attachmentportion bonded to the sensing wafer; and a sensing node, the sensingnode centered over the sensing portion of the sensing wafer, wherein thesensing node is isolated from the sensing portion of the sensing waferby a gap, and wherein the sensing node is isolated from the attachmentportion of the first silicon layer by a separation area; an insulatinglayer bonded to the first silicon layer opposite the sensing wafer; anda second silicon layer bonded to the insulating layer opposite the firstsilicon layer, the second silicon layer comprising: a first electricalcontact electrically connected with the sensing wafer; and a secondelectrical contact electrically connected with the sensing node.

The pressure sensor of the preceding paragraph can optionally include,additionally and/or alternatively, any one or more of the followingfeatures, configurations and/or additional components:

The pressure sensor includes a base wafer bonded to the backing waferopposite the sensing wafer.

The first electrical contact passes through the insulating layer andconnects to the first silicon layer.

The second electrical contact passes through the insulating layer andconnects to the sensing node of the first silicon layer.

The pressure sensor includes a reference sensing portion in the sensingwafer; a reference node in the first silicon wafer; a gap between thereference sensing portion and the reference node; and a third electricalconnection electrically connected to the reference node.

The pressure sensor includes at least one isolation slot in the secondsilicon layer, the isolation slot configured to electrically isolate thefirst electrical contact from the second electrical contact.

The insulating layer is in direct contact with the separation area.

The pressure sensor includes a topping wafer bonded to the secondsilicon layer opposite the insulating layer.

The pressure sensor includes one or more integrated circuit componentsbonded to the topping wafer opposite the second silicon layer.

The second silicon layer further comprises a structural portion, thefirst electrical contact embedded in the structural portion.

The pressure sensor includes a bond area between the attachment portionof the first silicon layer and the structural portion, the bond areabeing no greater than ten times the length of the gap between thesensing node and the sensing wafer.

The volume of the separation area is substantially larger than thevolume of the gap.

The volume of the isolation slot is substantially larger than the volumeof the gap.

The gap and the separation area contain a vacuum.

A method of making a capacitive pressure sensor includes depositing anitride layer on a silicon on insulator wafer; etching a sensing node ona first side of the silicon on insulator wafer; etching primary andsecondary cavities on a second side of the silicon on insulator waferopposite the first side; selectively removing the protective nitridelayer; bonding a sensing wafer to the first side of the silicon oninsulator wafer opposite the second side; bonding a backing wafer to thesensing wafer opposite the silicon on insulator wafer; and depositingmetal onto the primary cavities.

The method of the preceding paragraph can optionally include,additionally and/or alternatively, any one or more of the followingfeatures, configurations and/or additional components:

Depositing a nitride layer on the silicon on insulator wafer comprises:depositing a first nitride layer on the silicon on insulator wafer;etching a portion of the first nitride layer on the first side of thesilicon on insulator wafer; oxidizing the silicon on insulator wafer;stripping an oxide from a portion of the surface of the silicon oninsulator wafer; and depositing a second nitride layer on the firstportion.

The method includes patterning the first nitride layer before etching afirst portion of the first nitride layer.

The method includes selectively removing an oxide before depositingmetal onto the primary cavities.

The primary cavities are configured to receive electrical connection.

The secondary cavities are configured to isolate electrical connections.

While the invention has been described with reference to an exemplaryembodiment(s), it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted forelements thereof without departing from the scope of the invention. Inaddition, many modifications may be made to adapt a particular situationor material to the teachings of the invention without departing from theessential scope thereof. Therefore, it is intended that the inventionnot be limited to the particular embodiment(s) disclosed, but that theinvention will include all embodiments falling within the scope of theappended claims.

The invention claimed is:
 1. A capacitive pressure sensor comprising: abacking wafer; a sensing wafer comprising: a support portion bonded tothe backing wafer, and a sensing portion, the sensing portion configuredto detect pressure; and an electrode assembly comprising: a firstsilicon layer comprising: an attachment portion bonded to the sensingwafer; and a sensing node, the sensing node centered over the sensingportion of the sensing wafer, wherein the sensing node is isolated fromthe sensing portion of the sensing wafer by a gap, and wherein thesensing node is isolated from the attachment portion of the firstsilicon layer by a separation area; an insulating layer bonded to thefirst silicon layer opposite the sensing wafer; and a second siliconlayer bonded to the insulating layer opposite the first silicon layer,the second silicon layer comprising: a first electrical contactelectrically connected with the sensing wafer; and a second electricalcontact electrically connected with the sensing node.
 2. The pressuresensor of claim 1, further comprising a base wafer bonded to the backingwafer opposite the sensing wafer.
 3. The pressure sensor of claim 1,wherein the first electrical contact passes through the insulating layerand connects to the first silicon layer.
 4. The pressure sensor of claim1, wherein the second electrical contact passes through the insulatinglayer and connects to the sensing node of the first silicon layer. 5.The pressure sensor of claim 1, further comprising: a reference sensingportion in the sensing wafer; a reference node in the first siliconwafer; a gap between the reference sensing portion and the referencenode; and a third electrical connection electrically connected to thereference node.
 6. The pressure sensor of claim 1, further comprising atleast one isolation slot in the second silicon layer, the isolation slotconfigured to electrically isolate the first electrical contact from thesecond electrical contact.
 7. The pressure sensor of claim 1, whereinthe insulating layer is in direct contact with the separation area. 8.The pressure sensor of claim 1, further comprising a topping waferbonded to the second silicon layer opposite the insulating layer.
 9. Thepressure sensor of claim 8, further comprising one or more integratedcircuit components bonded to the topping wafer opposite the secondsilicon layer.
 10. The pressure sensor of claim 1, wherein the secondsilicon layer further comprises a structural portion, the firstelectrical contact embedded in the structural portion.
 11. The pressuresensor of claim 10, further comprising a bond area between theattachment portion of the first silicon layer and the structuralportion, the bond area being no greater than ten times the length of thegap between the sensing node and the sensing wafer.
 12. The pressuresensor of claim 1, wherein the volume of the separation area issubstantially larger than the volume of the gap.
 13. The pressure sensorof claim 6, wherein the volume of the isolation slot is substantiallylarger than the volume of the gap.
 14. The pressure sensor of claim 1,wherein the gap and the separation area contain a vacuum.
 15. A methodof making a capacitive pressure sensor comprising: depositing a nitridelayer on a silicon on insulator wafer; etching a sensing node on a firstside of the silicon on insulator wafer; etching primary and secondarycavities on a second side of the silicon on insulator wafer opposite thefirst side; selectively removing the protective nitride layer; bonding asensing wafer to the first side of the silicon on insulator waferopposite the second side; bonding a backing wafer to the sensing waferopposite the silicon on insulator wafer; and depositing metal onto theprimary cavities.
 16. The method of claim 10, wherein depositing anitride layer on the silicon on insulator wafer comprises: depositing afirst nitride layer on the silicon on insulator wafer; etching a portionof the first nitride layer on the first side of the silicon on insulatorwafer; oxidizing the silicon on insulator wafer; stripping an oxide froma portion of the surface of the silicon on insulator wafer; anddepositing a second nitride layer on the first portion.
 17. The methodof claim 16, further comprising patterning the first nitride layerbefore etching a first portion of the first nitride layer.
 18. Themethod of claim 16, further comprising selectively removing an oxidebefore depositing metal onto the primary cavities.
 19. The method ofclaim 16, wherein the primary cavities are configured to receiveelectrical connection.
 20. The method of claim 16, wherein the secondarycavities are configured to isolate electrical connections.